The adoption of commercial off-the-shelf (COTS) components is a cornerstone of the ‘New Space’ paradigm, driven by the requirement for accelerated development cycles, reduced costs, and enhanced performance in small satellite constellations and low Earth orbit (LEO) missions. Within this framework, traditional approaches based on expensive, radiation-hardened components are often bypassed, as continuous availability may not be a critical requirement.

However, utilizing COTS components introduces significant risks—primarily regarding radiation susceptibility, unknown reliability, and a lack of traceability—given that these devices are designed for terrestrial applications rather than the extreme conditions of space. Consequently, COTS devices are highly vulnerable to thermal cycling, vacuum outgassing, and, most critically, radiation-induced failures such as total ionizing dose (TID) degradation and single-event effects (SEE). Among these, Single-Event Latch-up (SEL) poses a catastrophic risk, as it can lead to permanent device destruction and the subsequent compromise of the mission.

Accordingly, the rapid adoption of COTS has catalyzed a shift from traditional board-level SEL mitigation toward chip-level protection to minimize subsystem downtime. Nevertheless, contemporary protection devices often exhibit excessive complexity, high power consumption, and a significant PCB footprint, which complicates the implementation of granular, device-specific protection. Furthermore, static protection schemes fail to account for the gradual increase in leakage current caused by TID, resulting in a critical trade-off between false-positive SEL detection and ‘protection blindness’ against micro-latch-ups as the mission progresses.

To tackle these limitations, this webinar introduces SELPROTECT: a low-complexity, asynchronous integrated circuit (IC) specifically designed for granular, chip-level protection. Fabricated using 180nm High-Voltage CMOS SOI technology, the device features several key innovations:

• Integrated Sensing Architecture: The design eliminates the need for external sensing components, significantly reducing both pin count and the required PCB area.
• Dual-Mode Autonomous Training: The IC incorporates specialized current and time training modes to characterize the unique operational current signature of the protected device.

As a result, SELPROTECT can dynamically recalibrate its detection thresholds in-orbit. This capability allows the system to effectively compensate for TID-induced aging while ensuring high-speed, low-power protection against destructive SEL events.