Webinar: UCIe vs. BoW: Your Essential Guide to Choosing the Right Chiplet Standard by Horizon House Publications

UCIe vs. BoW: Your Essential Guide to Choosing the Right Chiplet Standard

About

As chiplet-based architectures become essential for high-performance computing (HPC) and artificial intelligence (AI), efficient die-to-die (D2D) communication is critical to meeting the demands of modern chiplet systems. This webinar delves into how the UCIe 2.0 and BoW (Bunch of Wires) standards facilitate better signal integrity in chiplet interconnect, enabling designers to tackle the challenges in complex chiplet systems.
Through practical examples, we will explore the key features of these interconnect standards and their role in supporting the growth of chiplet interconnects. Participants will gain insights into using electronic design automation to simulate their chiplet system integration, leveraging these technologies to enhance system-level signal integrity.
Join us to deepen your understanding of UCIe and BoW and learn how to effectively apply these standards in designing scalable, modular chiplet systems for next-generation computing.

Presenter

Chun-ting "Tim" Wang Lee, Ph.D.

Signal Integrity Application Scientist, Keysight

Chun-ting "Tim" Wang Lee, Ph.D., is a Signal Integrity Application Scientist at Keysight, where he uses simulation tools and measurement insights to help engineers achieve better Signal Integrity (SI) in their designs. In his current role, he has been studying the Chiplet UCIe standard and has delivered presentations on the system-level SI challenges associated with chiplet designs. Recognized as one of DesignCon’s 40-under-40, Tim is known for his technical knowledge and clear and engaging communication style at industry conferences. He holds a Ph.D. in Signal Integrity from the University of Colorado at Boulder, focusing on achieving better simulation and measurement correlation for printed circuit board SI analysis. Tim's mission is to empower engineers with the knowledge and tools to confidently tackle signal integrity and chiplet design challenges.

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