Webinar: Stress Testing PCIe 6.0 FLIT-based Forward Error Correction by Horizon House Publications

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Stress Testing PCIe 6.0 FLIT-based Forward Error Correction

About

PCIe 6.0 introduces Flow Control Unit (FLIT) encoding to allow forward error correction (FEC) on fixed-size packets. Stress testing PCIe hardware includes addressing this new protocol approach. Once FLIT mode is turned on, it will work with any data rate. It improves overall bandwidth and provides low latency, so it is important that hardware is properly tested. This webinar addresses:

Correlation between uncorrectable errors and FBER using FLIT FEC.

FLIT FEC evaluation analysis method for the Physical Layer under worst-case Rx test conditions.

Chip and module-level improvement recommendations with respect to uncorrectable error pattern dependency and bit-sequence repeatability.

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Presenter

Hiroshi Goto

BERT and Optics Specialist/Sr. Business Development Manager, Anritsu

Hiroshi Goto has over 25 years of experience as a high speed and optical Engineer at Anritsu Company holding a variety of positions, including Design Engineer, Product Marketing Engineer and currently high speed and optical Product Manager and Business Development Manager. Mr. Goto holds a Bachelor’s degree in Physics from Aoyama Gakuin University in Tokyo Japan. He resides in the Dallas area and has authored numerous industry application notes and white papers and frequently speaks on the topic of signal integrity.

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