As the industry starts to shift from 112G to 224G PAM-4 systems, organizations like the Ethernet Alliance, SNIA, OIF, and IEEE are already looking to the next generation with 448G per lane data rates. While signal integrity issues with cabling, connectors, and modules are being addressed quickly, IC substrates and land patterns on the PCB remain a bottleneck to ensuring signal integrity at 224G and 448G.
Based on results in the literature and work done by the author, this presentation shows why UHDI design and manufacturing will be a requirement to support 224G and 448G per lane data rates. The results illustrate how materials influence signal integrity in UHDI builds, and how via/transmission line designs at UHDI feature sizes impact signal propagation in IC substrates and the PCB.
The specific bandwidth and noise margin requirements for 448G will depend on the chosen modulation format. Based on simulation results for via structures and transmission lines at UHDI feature sizes, we can compare the available channel bandwidth with the required bandwidth for PAM-6 or PAM-8 modulation. From the PCB/packaging perspectives, it appears that PAM-8 is an optimal modulation format that balances higher bandwidth against tighter noise margins in M-ary PAM signaling.