Power integrity problems tend to show up late. A board passes layout review, and then a device at the far end of a rail browns out under load, or supply noise starts causing failures that are hard to trace. More often than not, the cause is the power delivery network. Either there’s too much DC voltage drop across planes and vias, or PDN impedance isn’t low enough at the frequencies that matter.

In this webinar, Clint Patton, Team Lead for Electromagnetic Simulation at GoEngineer, covers the fundamentals of power integrity and shows how to analyze them in CST Studio Suite. The session starts with how the PDN works, what causes DC IR drop, and how plane impedance, decoupling capacitors and mounting inductance affect AC performance. Clint then takes an example board through a complete power integrity workflow, from setup to IR drop and PDN impedance results, and shows how decap analysis can guide better capacitor selection and placement.

Topics include:

• Power delivery network fundamentals


• DC IR drop analysis


• AC PDN impedance, including power plane impedance and decap mounting inductance


• Setting up and running a power integrity analysis in CST Studio Suite


• Using the Decap Analysis Tool to evaluate and improve your decoupling strategy

This session is a good fit for PCB designers, hardware engineers and SI/PI specialists who want a practical look at finding power integrity issues before a board goes to fab.