Webinar: PCIe 5.0 Post-Layout Verification in MATLAB by Horizon House Publications

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PCIe 5.0 Post-Layout Verification in MATLAB

About

In this webinar, we will explore post-layout verification of a high-speed serial printed circuit board (PCB) created in Cadence® Allegro. We will demonstrate how to analyze multiple PCIe 5.0 channels using IBIS-AMI models and loopback boards to determine eye diagram performance and margins. The webinar will cover PCB import, setup, simulation, and effective debugging techniques.

Highlights of the webinar include:

Importing and setting up PCB databases.

Setting up a multi-board simulation.

Simulating over 200 PCIe 5.0 channels.

Analyze results and debug closed eye diagrams.

By the end of the webinar, you will have a comprehensive understanding of Signal Integrity Toolbox and its practical application for PCB post-layout verification, enabling you to effectively diagnose and resolve signal integrity issues.

Please Note: By registering for this webinar, the details of your profile may be used by Signal Integrity Journal™, the presenter, and the sponsor to contact you by email.

Presenter

Andy Zambell

Sr. Product Marketing Engineer, MathWorks

Andy Zambell is a Sr. Product Marketing Engineer for SerDes and Signal Integrity applications at MathWorks. Prior to joining MathWorks, Andy was a Signal Integrity Engineer at FCI USA LLC and Amphenol for a decade where he specialized in new product development and customer support of high-speed backplane connectors. He also was involved in the development of industry standards such as SAS, IEEE 802.3 and OIF CEI. He received a B.S in Physics from Lebanon Valley College and an M.E. in Electrical Engineering from Penn State University.

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