KEYNOTE: S + I = $ - How to Succeed at a Career in Signal Integrity

Run time: 0:00:00 – 0:57:32

Presented by: Donald Telian, Signal Integrity Consultant

1pm ET

What is the signal integrity engineer’s job description? We make electronics work faster. But how do we do that? Interestingly, after doubling data rates more than a dozen times, in this keynote Donald Telian reveals the answer is always changing. As such, to succeed in signal integrity you must learn to creatively adapt – daily. And you must do this both technically and organizationally. This unique talk blends data-rate-dependent SI design guidance with the three keys to succeeding at a career in signal integrity, revealing the answers are less intuitive and more fun than you thought.

Presenter Bio:


Donald Telian has worked in signal integrity for more than 40 years, uniquely positioning him to speak about a career in SI. He has invented various SI concepts, tools, and quirks engineers use every day to get their jobs done. He is an SI coach, the owner of SiGuys.com, and the author of Signal Integrity, In Practice
– a new book that cuts through the noise to explain how to “do” SI when confronted with the data rates of today.


A Systematic Methodology for DDR5 SI Analysis

Run time: 0:58:30 – 1:55:25

2pm ET

Presented by: Dirgha Khatri, Principal Signal Integrity Engineer, Micron and Pankaj Ahirwar, Principal Signal Integrity Engineer, Micron

The storage and computing demands of cutting-edge solutions, such as AI/ML, automotive, enterprise, and storage applications are driving Micron DRAM products to operate at unprecedented speed limits. This webinar will discuss how Micron utilizes Cadence system simulation tools to perform accurate SI analysis, which is essential for minimizing failures and guaranteeing reliable performance. The webinar will also cover SI challenges encountered at different stages of system-level analysis.


Presenter Bios:

Dirgha joined the Micron Communication subsidiary of Micron in February 1997 as an antenna engineer, where he worked on designing antennas in RFID tags. Then he started a carrier analyzing and optimizing both SI/PI from an early series of DIMM designs in finding solutions for higher speeds with both SDP/DDP DRAM packages. He was also involved in analyzing custom DIMMs like CDIMMs, DDIMMs, and standard JEDEC DIMMs. Dirgha is currently a principal engineer in CEG Signal Integrity R&D, group where he is leading and managing the DIMMs simulation team. Dirgha earned his MSEE from the University of Alaska Fairbanks in 1996. He currently holds six patents.



Pankaj joined Micron in December 2022 as a principal signal integrity engineer in the CEG Signal Integrity R&D group. Prior to Micron, he worked as a signal/power integrity engineer at Cadence and Marvell (Boise), among others. At Micron Pankaj works on system-level SI/PI analysis for various DIMM architecures, optimizing designs for higher speed solutions and power architecture analysis. He received his BSEE from The Indian institute of Technology, Roorkee and holds a PhD in semiconductor device physics from The University of New Mexico.


Signal Integrity Signoff Methodology for a Multi-chiplet Package

Run time: 1:56:20 – 2:44:02

Presented by: Suresh Subramaniam, Systems/Packaging Lead, Apex and Abhiram Chandrashekar, System Analysis Engineer, Apex

3pm ET

Apex Semiconductor has developed an industry-first chiplet based a SmartNIC platform composed of a CXL I/O hub and two eight-core RISC-V processors, in conjunction with our ecosystem partners, DreamBig, Ventana microsystems, and BlueCheetah. We have employed the Bunch of Wires (BoW) Open Die-to-Die (D2D) standard as the interconnect of choice between the chiplets. Each D2D link has a bi-directional bandwidth of one Tb/s. In addition, the platform supports network connectivity with x40 PCIe Gen-5 and 800 Gb/s (x8 112Gbps) Ethernet, both of which can be flexibly configured. This three-chiplet SmartNIC SiP is realized in an organic substrate. In this talk, we present a signal integrity signoff methodology for the three high-speed interfaces on this platform, using the Cadence^® Sigrity™ tool suite.


Presenter Bios:


Suresh Subramaniam's professional experience includes senior engineering roles at Xilinx, AMD, Applied Micro, Ericsson, and several startups. His interests are in signal and power integrity, advanced packaging and systems design; SoC, chiplets, and I/O subsystem architecture. He has been actively involved in the OCP ODSA sub-project and is a member of the DesignCon Technical Program Committee. He holds 12 patents.

Abhiram Chandrashekar is an experienced systems analysis engineer, specializing in advanced packaging techniques and SI/PI analysis for complex systems. With prior experience at Ampere Computing and AppliedMicro as a principal circuit engineer, he was responsible for designing high-speed circuits and clock distribution networks for high-performance 64-bit ARM v8 multi-core processors.


Seamless Design and Analysis for 112G System Interfaces

Run time: 2:44:37 – 3:37:04
Presented by: Yun Chase, Solutions Architect, Cadence

4pm ET

As 112G+ interfaces are used in more applications, system design teams will face the challenge of optimizing the interconnect between the transceivers. Meeting industry compliance specifications requires analysis of device models with equalization techniques, and of all sections of the signal path including IC package, PCB, high-speed connectors, and/or cables. This overview will present Cadence design and analysis tool workflows that address the challenges and reduce engineering time in optimizing high-speed interconnect and equalization setup to meet bit-error rate, COM, and other signal integrity requirements.


Presenter Bio:

Yun Chase is currently a product engineer responsible for multi-physics systems analysis focused on advancing signal and power integrity solutions capabilities. Previously, he served several years as an applications engineer at Sigrity (now Cadence), as well as Siemens EDA (formerly Mentor Graphics). He also held a hardware engineering position at Marvell focused on signal and power integrity for PCB and IC/PKGs that include high speed DDRx bus, as well as multi-gigabit SerDes interfaces.  Chase holds a BS in physics and an MS in mechanical engineering from Georgia Tech.

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