Massive processors for big data, AI, and 100+ Gigabit communications are already reaching 2000 Amps on their core power rails. The next generation of AI/ML ASICs will reach 5000 Amps in just a few more years. This presentation will discuss critical aspects of designing, simulating, and measuring high-current power rails and assessing available topologies to balance performance and cost trade-offs. You will learn how to:
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