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WEBINAR ENDED
Wed, May 5, 2021 · 1:27 PM · 1 hour

FPGA, ASIC, and SoC Design

Wed, May 5, 2021 · 1:27 PM · EDT
Note: This webinar is part of the multi-session recurring webinar FPGA, ASIC, and SoC Design.
About This Webinar

Attend the FPGA, ASIC, and SoC Design track and learn how to use MATLAB and Simulink to model and simulate SoC architecture, partition your design components and test bench for reusability, and eliminate bugs before prototyping or handoff. Learn about behavioral modeling and simulation of mixed-signal systems in Simulink, and hear from Cadence about the latest advances in the integrated MATLAB and Virtuoso ADE workflow. In addition, discover how to rapidly prototype image processing applications and generate hardware agnostic HDL code that can be used for deployment to FPGAs and ASIC.

Who can view: Everyone
Webinar Price: Free
Hosted By
MATLAB EXPO webinar platform hosts FPGA, ASIC, and SoC Design
MATLAB EXPO's webinars
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